1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device provided with an input buffer or an output buffer.
2. Description of Related Art
In these years, since a variety of semiconductor devices have been manufactured, it has often been required to realize a level shift of amplitude of a signal to the semiconductor device at the time of connecting these semiconductor devices in accordance with an input level and output level. Therefore, attention is paid to the technology to give a level shift function to an input buffer and an output buffer of semiconductor device. An example of this technology will be explained below using USB2.0.
As the interface specification for connection between a personal computer and peripheral devices thereof, USB2.0 (Universal Serial Bus) is used. For this SB2.0, three kinds of transfer mode of HS (High Speed), FS (Full Speed), and LS (Low Speed) are prepared. Particularly, in the HS mode, remarkable high speed (480 Mbps) data transfer can be realized in comparison with USB1.1 of the related art.
FIG. 8 shows a USB input/output circuit 80 combining an HS circuit for transferring data signal in the HS mode and an FS/LS circuit for transferring data signal in the FS or LS mode. The USB input/output circuit 80 includes an HS output circuit 81, an HS input circuit 82, an FS/LS output circuit 83, and an FS/LS input circuit 84. Outputs of the HS output circuit 81 and FS/LS output circuit 83 and inputs of the HS input circuit 82, FS/LS input circuit 84 are connected with wires at an input/output terminal D+ and input/output terminal D−. Moreover, a data input terminal DATA, an enable terminal ENABLE, a clock input terminal CLOCK, and a mode switching terminal MODE are connected respectively to the HS output circuit 81, HS input circuit 82, FS/LS output circuit 83, and FS/LS input circuit 84. Owing to the structure explained above, the USB input/output circuit 80 can input/output the data to and from the input/output terminal D+ and input/output terminal D−.
FIG. 9 shows an HS output circuit 81 provided within the USB input/output circuit 80 shown in FIG. 8. A logic circuit 91 inputs a data signal DS to be inputted to the data input terminal DATA and outputs a data signal DS on the basis of the mode switching signal MS and the clock signal CS. A pre-buffer 92 drives the data signal DS outputted from the logic circuit 91 on the basis of a first power supply voltage VDD1. A shutdown circuit 93 controls conductive state between the pre-buffer 92 and the main buffer 94 on the basis of the mode switching signal MS inputted to the mode switching terminal MODE. The main buffer 94 inputs the data signal DS outputted by the pre-buffer 92 via the shutdown circuit 93 and outputs the amplified data signal DS to the input/output terminals D+, D− on the basis of a second power supply voltage VDD2 higher than the first power supply voltage VDD1.
This HS output circuit 81 of the related art conducts operations of the FS/LS mode or HS mode as will be explained below. In the case of FS/LS mode (refer to T0 to T1 in FIG. 10), the shutdown circuit 93 enters the off-state on the basis of an input of the mode switching signal MS, for example, of “H” level. Therefore, the shutdown circuit 93 cuts off a signal path between the pre-buffer 92 and the main buffer 94. Therefore, a voltage outputted by the FS/LS circuit is impressed (refer to FIG. 8) to the input/output terminals D+, D− connected to the main buffer 94. Meanwhile, in the case of the HS mode, (refer to T1′ to T2 in FIG. 10), the shutdown circuit 93 enters on-state on the basis of input of the mode switching signal MS, for example, of “L” level. Accordingly, the data signal DS outputted by the pre-buffer 92 is inputted to the main buffer 94 via the shutdown circuit 93.
As explained above, in the HS output circuit 81 of the related art, the shield circuit 93 enters on-state or off-state on the basis of the mode switching signal MS. In the HS mode, the data signal DS inputted to the data input terminal DATA is outputted to the input/output terminals D+, D− connected to the main buffer 94.
As the related arts, the patent document I discloses a semiconductor device (refer to FIG. 12) wherein a switch N124 is provided between a logic circuit 121 in a preceding stage to be operated with a first power supply voltage and a logic circuit 122 in a subsequent stage to be operated with a second power supply voltage higher than the first power supply voltage.
[Non-patent document 1] “USB Complete SIB Access” by Acserson and Jan (translated by Insight International), Sold by Seiunsha Publishing Co., Ltd.; P380, Chapter 210 Electrical Interface Circuit (USB Transceiver)
[Patent document 1] Japanese Laid Open Patent Application Hei 10(1998)-308098
However, in the HS output circuit 81 shown in FIG. 9, a spike-wise noise has been generated in a signal outputted from the pre-buffer 92 when the mode is switched to the HS mode from the FS/LS mode.
FIG. 11 shows partially enlarged pre-buffer 92, shutdown circuit 93, and main buffer 94 within the HS output circuit of a related art. In a PMS transistor P94 provided in the main buffer 94, a parasitic capacitance C is formed. Here, when the mode is switched to the HS mode from the FS/LS mode, a transfer gate constituted with the PMOS transistor P95 and the NMOS transistor N93 is turned to the on-state from the off-state. Therefore, a voltage applied to a gate of the PMOS transistor P94 is shifted from the second power supply voltage VDD2 to the first power supply voltage VDD1 lower than the second power supply voltage VDD2. Therefore, charges accumulated in the parasitic capacitance C flow into an inverter INV92 via the transfer gate. In this timing, a signal of “L” level outputted by the logic circuit 91 is inputted to the inverter INV92. Therefore, the PMOS transistor P92 of the inverter INV92 is in the on-state. Accordingly, charges accumulated in the parasitic capacitance C flow into the first power supply voltage VDD1 via the PMOS transistor P92. Namely, in the period of T1 to T1′ shown in FIG. 10, voltage of the signal outputted from the inverter INV92 is raised with such inverse current. A spike noise generated in this timing exceeds voltage resistance of the NMOS transistor N92, resulting thereby deterioration of characteristic or electrical breakdown of the NMOS transistor N92. Particularly, in the case where INV92 including the NMOS transistor N92 is designed under the voltage resistance corresponding to the power supply VDD1 (should be lower than VDD2), probability of occurrence of characteristic deterioration and electrical breakdown becomes distinctive.
Moreover, even in the semiconductor device described in the patent document 1, an inverse current is generated toward the first power supply voltage from the second power supply voltage and thereby a spike noise is generated, resulting in the problems explained above, in the case where the signal of “H” level is transferred to the logic circuit 122 in the subsequent state from the logic circuit 121 of the preceding stage.